Testing digital circuits is extremely important. Based on design and simulation results, sets of test vectors are generated for application to prototype circuits, and often test fixtures need to be customized, depending on operational characteristic of the circuit inputs and outputs. With synchronous circuits, propagation delays and timing closure are of particular concern.
For testing the interaction between discrete components, the situation is relatively straightforward. For example, U.S. Pat. No. 4,926,425 discloses a system for testing digital circuits, wherein test node equipment is provided between successive component groups operating in cascade.
A single-chip integrated circuit however, for example an Application Specific Integrated Circuit (ASIC), typically contains high speed sequential (core) logic, and input and output combinational logic stages surrounding the core logic and connected to respective input and output pads. Generally, the input and output stages cannot run as fast as the core logic, primarily due to input and output parasitic capacitances, which imposes some severe limitations on "At-Speed"or "AC"testing of the core logic.
In the prior art, various approaches to testing have been proposed. For example:
U.S. Pat. No. 4,638,246 discloses an integrated circuit input-output diagnostic system for detecting open connections at the input and output pads. Input activity and output load detector circuits are provided on-chip for this purpose.
U.S. Pat. No. 4,477,902 discloses a testing method for assuring AC performance of high performance random logic designs using a low speed tester. Outputs are strobed once every cycle, and the patent does not deal with I/O noise and cycle time limitations due to tester pin capacitances and tester edge placement inaccuracy.
In contrast thereto, in the present invention outputs are strobed every "N"cycles, where "N"is a number higher than two, and the insertion of a dead cycle before strobing allows output ringing to settle. Further, three-stating of the outputs during the clock burst mode reduces the possibility of double clocking caused by many outputs switching at the same time.
U.S. Pat. No. 4,813,001 discloses an AC calibration method for determining the transfer function of a data acquisition system. This patent relates to calibration and transfer function determination for linear systems and analog devices such as data acquisition systems.
In contrast thereto, the present invention is a methodical approach to noise reduction and at-speed testing of digital integrated circuits.
U.S. Pat. No. 4,870,345 discloses a semiconductor integrated circuit device which includes cascaded asynchronous sequential logic circuits. Scanning shift registers are provided between the asynchronous sequential circuits to permit test data to be applied to the inputs of the circuits and to latch and shift out output data provided by the circuits in response to the test data.
U.S. Pat. No. 4,764,926 discloses an integrated circuit having a built-in test facility, the integrated circuit being partitioned into a number of sub-circuits each of which comprises a combinational logic circuit and a register.
U.S. Pat. No. 4,800,564 discloses error detection and fault isolation in a high performance clock system in a data processor or the like. This patent describes means to detect faults on the clock line, which is only one of the possible nets in a design, and requires hardward (logic) implementation inside the chip to detect faults.
In contrast thereto, the present invention is not limited to the testing of a single net, and does not require any unique logic implementation for detection of AC faults.
The following references are exemplary of prior art digital logic test equipment:
U.S. Pat. No. 4,928,278 discloses an IC test system wherein timing errors of each of a number of tester pin electronics units is executed in parallel among the units or blocks thereof.
U.S. Pat. No. 4,726,025 discloses a timing cycle generator and verifier in which a PROM stores the timing constants that are employed by the generator. Two modes of operation are discussed.
U.S. Pat. No. 4,705,970 discloses a programmable interval
Application Note, "Automated Digital Signal Processing" (Massachusetts Computer corporation, 080-00976-00 0887-976) discloses a data acquisition user interface wherein a "virtual instrument"controls data acquisition and transmission devices, sampling rates, data display, file I/O multiplexing and demultiplexing, data flow and basic signal processing.